This invention relates in general to digital data transmissions among different substations or nodes. More specifically, the invention relates to data receiving and demodulation of encoded data signals which have both a data and a clock or reference component.
Many high speed communication systems have nodes which are operatively connected with a single common transmission line. This arrangement implies that only one station or node may communicate with another at any one time. When all nodes have to communicate, the signals arrive in groups. Higher signaling rates are thus necessary which require fast clock recovery circuitry in order to provide accurate signaling.
Traditionally, a modulated data signal was filtered and amplified and then passed to the input of a multiplier. Another circuit removed the clock signal and it was also passed to the input of the multiplier. The clock recovery was often accomplished with a circuit known as a phase lock loop. This circuit, however, had serious shortcomings in high speed data handling because of its iterative method. It generally included relatively complex and expensive circuitry, and required frequent maintenance and tuning. At the higher signal rates, the phase lock loop also had trouble in reproducing accurate error-free information.
Various techniques have been used to transmit and receive encoded data along a common transmission line. None have been completely satisfactory. One such system is illustrated in U.S. Pat. No. 4,287,596, which is hereby incorporated by reference. As explained therein, a technique is used which is known as phase encoded signals with a biphase-level code (Manchester code). While the system had advantages over phase lock loops, it still requires relatively complex circuitry and it is limited for use with phase-encoded signals.
This invention has particularly found a system and method for receiving and demodulating digital information at a node which allows relatively simple circuitry and which yields fast, accurate data and clock recovery. In particular, this invention utilizes a phase-coherent frequency shift keying (FSK) modulated signal which is not described in U.S. Pat. No. 4,287,596.
The accuracy of demodulation and clock recovery in this invention is higher with the use of 90-degree delay lines instead of 270 degrees as used in U.S. Pat. No. 4,287,596. Characteristics of the FSK system are set forth in An American National Standard, IEEE Standards for Local Area Networks: Token-Passing Bus Access Method and Physical Layer Specifications. As stated at page 176 therein, FSK is a modulation technique whereby information is impressed upon a carrier by shifting the frequency of the transmitted signal to one of a small set of frequencies. Phase-coherent FSK is a particular form of FSK where the two signaling frequencies are integrally related to the data rate and transitions between the two signaling frequencies are made at zero-crossings of the carrier waveform.
Another key feature of this invention is that it can demodulate either the original signal or its complement (a signal 180 degrees out of phase). The receiver operates in a transparent manner with either the signal or its complement. This feature is particularly important because the signals in large data handling systems are often inadvertently omitted.
Phase-coherent FSK has been found particularly advantageous in handling large quantities of serially produced high speed data. The different carrier frequencies of the FSK signal have a tendency to produce distinctive error-free, noiseless data and clock signals which can be relatively quickly and easily recovered.